Для початку декілька скріншотів та фото.

Рис.1 Місце плати Catapult v2 в лінійці FPGA прискорювачів Майкрософт.
Рис.2 (Перше фото) 5 жовтня 2016 рік, Doug Burger демонструє
Catapult v2.
Скріншот з YouTube. (Друге фото) Майкрософт... Пошук... і без песика 🐕 - непорядок! Осінь 2019 рік, плата прибула з
eBay і готова до використання.
Невеличка цитата з
інтерв'ю Doug Burger, 9 травня 2018 року:
"Host: I was just going to say, is this now in research, is it beta, is it production? Where are you with it?
Doug Burger: In late 2015, Microsoft started shipping one of the Catapult FPGA boards in almost every new server that it bought. That’s in Bing, Azure and other properties. And so, by this point, we’ve gone to very large scale. This stuff is deployed at ultra-large scale worldwide.
We’re one of the largest consumers of FPGAs on the planet..."
1. Огляд
1.1 Основні компоненти
1.2 Маркування та посилання
U1 - FPGA
Stratix V
U2 - 25Q256A
Micron Serial NOR Flash Memory
U3 - FT232HL
Single Channel HiSpeed USB to Multipurpose UART/FIFO IC
U4 - OSC3 IDT8N4Q001
Quad-Frequency Programmable Clock Oscillator
U5 - TMP411
Remote and Local Temperature Sensor
U16 - 4128BWP
128-Kbit serial I²C bus EEPROM
U46,48,50,52,54,56,58,60,62 -
H5TC4G83BFR-PBA SK hynix 4Gb 1.35V DDR3L SDRAM
PU12 - s1010
ES1010SI 12V Hot-Swap Power Distribution Controllers
2. Живлення
3. Завантаження конфігураційного файла(програмування) FPGA Stratix V
Існує два методи програмування:
- Програмування JTAG:
Конфігурація завантажується безпосередньо в FPGA Stratix V, з застосуванням інтерфейсу JTAG. FPGA збереже свій статус до тих пір, поки на плату буде подано живлення, інформація про конфігурацію буде втрачена при відключенні живлення.
- AS програмування:
Іншим методом програмування є активна послідовна конфігурація. Конфігураційний потік завантажується на пристрій EPCQ256, який забезпечує його енергонезалежне зберігання. Інформація зберігається в EPCQ256, навіть якщо плата вимкнена. Коли плата увімкнена, дані конфігурації з EPCQ256 автоматично завантажуються в FPGA Stratix V.
3.1 Програмування JTAG
3.2 AS програмування
4. Периферія підключена до FPGA.
У цьому розділі описані інтерфейси переферійних пристроїв, що підключені до FPGA.
Користувачі можуть керувати та контролювати переферійні пристрої зі сторони FPGA.
4.1 Quad-Frequency Programmable Clock Oscillator
Pin | Name | Type | Description | FPGA | FPGA bsdl |
1 | DNU | | Do not use. | 2.5V | - |
2 | OE | Input-Pullup | Output enable pin. LVCMOS/LVTTL interface levels. | 2.5V | |
3 | GND | Power | Power supply ground. | - | - |
4 | FSEL0 | Input-Pulldown | Default frequency select pins. LVCMOS/LVTTL interface levels. | 0V | |
5 | FSEL1 | Input-Pulldown | Default frequency select pins. LVCMOS/LVTTL interface levels. | 0V | |
6 | Q | Output | Differential clock output. LVDS interface levels. | ? | |
7 | nQ | Output | Differential clock output. LVDS interface levels. | ? | |
8 | VDD | Power | Power supply pin. | - | - |
9 | SDATA | Input-Pullup | I2C Data Input. LVCMOS/LVTTL interface levels. | PIN_N7 | 1350 |
10 | SCLK | Input-Pullup | I2C Data Input. LVCMOS/LVTTL interface levels. | PIN_P7 | 1353 |
4.2 128-Kbit serial I²C bus EEPROM
Pin | Name | Type | Description | FPGA | FPGA bsdl |
1 | E0 | Input | Chip Enable | | |
2 | E1 | Input | Chip Enable | | |
3 | E2 | Input | Chip Enable | | |
4 | VSS | Ground | Ground | - | - |
5 | SDA | I/O | Serial Data | | |
6 | SCL | Input | Serial Clock | | |
7 | ~WC | Input | Write Control | | |
8 | VCC | Supply voltage | Supply voltage | - | - |
4.3 Remote and Local Temperature Sensor
Pin | Name | Type | Description | FPGA | FPGA bsdl |
1 | V+ | Power supply | Positive supply (2.7 V to 5.5 V) | - | - |
2 | D+ | Analog input | Positive connection to remote temperature sensor | | |
3 | D- | Analog input | Negative connection to remote temperature sensor | | |
4 | ~THERM | Digital output | Thermal flag, active low, open-drain; requires pull-up resistor to V+ | | |
5 | GND | Ground | Ground | - | - |
6 | ~ALERT/~THERM2 | Digital output | Alert (reconfigurable as second thermal flag), active low, open-drain; requires pullup resistor to V+ | | |
7 | SDA | Digital input/output | Serial data line for SMBus, open-drain; requires pull-up resistor to V+ | PIN_AV26 | 2520 |
8 | SCL | Digital input | Serial clock line for SMBus, open-drain; requires pull-up resistor to V+ | PIN_AW26 | 2511 |
4.4 LED
LEDG[0] | PIN_A11 | | |
LEDG[1] | PIN_A10 | | |
LEDG[2] | PIN_B10 | | |
LEDG[3] | PIN_C10 | | |
LEDG[4] | PIN_C9 | | |
LEDG[5] | PIN_C8 | | |
LEDG[6] | PIN_B8 | | |
LEDG[7] | PIN_A8 | | |
4.5 QSFP Transceiver
QSFP Transceiver Pinout
Pin | Logic | Symbol | Name/Description | QSFP#0 | QSFP#1 |
1 | | GND | Ground | - | - |
2 | CML-I | Tx2n | Transmitted Inverted Data Input | GXB_TX_R11 | GXB_TX_R15 |
3 | CML-I | Tx2p | Transmitted Non-inverted Data Input | GXB_TX_R11 | GXB_TX_R15 |
4 | | GND | Ground | - | - |
5 | CML-I | Tx4n | Transmitted Inverted Data Input | GXB_TX_R13 | GXB_TX_R17 |
6 | CML-I | Tx4p | Transmitted Non-inverted Data Input | GXB_TX_R13 | GXB_TX_R17 |
7 | | GND | Ground | - | - |
8(6) | LVTTL-I | ModSeiL | Module Select | ? | ? |
9(1) | LVTTL-I | ResetL | Module Reset | ? | ? |
10 | | Vcc Rx | +3.3 VDC Receiver Power Supply | - | - |
11(3) | LVCMOS-I/O | SCL | Serial Clock for I2C Interface | PIN_AB24(2409) | PIN_AA25(2475) |
12(2) | LVCMOS-I/O | SDA | Serial Data for I2C Interface | PIN_AC24(2406) | PIN_AB25(2484) |
13 | | GND | Ground | - | - |
14 | CML-O | RX3p | Receiver Non-inverted Data Output | | |
15 | CML-O | RX3n | Receiver Inverted Data Output | | |
16 | | GND | Ground | - | - |
17 | CML-O | RX1p | Receiver Non-inverted Data Output | | |
18 | CML-O | RX1n | Receiver Inverted Data Output(RED DOWN) | | |
19 | | GND | Ground | - | - |
20 | | GND | Ground | - | - |
21 | CML-O | RX2n | Receiver Inverted Data Output(RED UP) | | |
22 | CML-O | RX2p | Receiver Non-inverted Data Output | | |
23 | | GND | Ground | - | - |
24 | CML-O | RX4n | Receiver Inverted Data Output | | |
25 | CML-O | RX4p | Receiver Non-inverted Data Output | | |
26 | | GND | Ground | - | - |
27(5) | LVTTL-O | ModPrsL | Module Present | ? | ? |
28(4) | LVTTL-O | IntL | Interrupt | ? | ? |
29 | | Vcc Tx | +3.3 VDC Transmitter Power Supply | - | - |
30 | | Vcc1 | +3.3 VDC Power Supply | - | - |
31(7) | LVTTL-I | LPMode | Low Power Mode | ? | ? |
32 | | GND | Ground | - | - |
33 | CML-I | TX3p | Transmitted Non-inverted Data Input | GXB_TX_R12 | GXB_TX_R16 |
34 | CML-I | TX3n | Transmitted Inverted Data Input | GXB_TX_R12 | GXB_TX_R16 |
35 | | GND | Ground | - | - |
36 | CML-I | TX1p | Transmitted Non-inverted Data Input | GXB_TX_R10 | GXB_TX_R14 |
37 | CML-I | TX1n | Transmitted Inverted Data Input | GXB_TX_R10 | GXB_TX_R14 |
38 | | GND | Ground | - | - |
4.6 DDR3L SDRAM
DDR3L SDRAM
Pin | Logic | Symbol | Name/Description | U46 | Uxx |
A1 | Supply | VSS | Ground | - | - |
A2 | Supply | VDD | Power Supply | - | - |
A3 | | NC | No Connect | - | - |
A7 | Output | NF/~TDQS | Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. | | |
A8 | Supply | VSS | Ground | - | - |
A9 | Supply | VDD | Power Supply | - | - |
B1 | Supply | VSS | Ground | - | - |
B2 | Supply | VSSQ | DQ Ground | - | - |
B3 | Input/Output | DQ[0] | Data Input/Output: Bi-directional data bus | | |
B7 | Input | DM/TDQS | Input Data Mask: DM is an input mask signal for write data. | | |
B8 | Supply | VSSQ | DQ Ground | - | - |
B9 | Supply | VDDQ | DQ Power Supply | - | - |
C1 | Supply | VDDQ | DQ Power Supply | - | - |
C2 | Input/Output | DQ[2] | Data Input/Output: Bi-directional data bus | | |
C3 | Input/Output | DQS | Data Strobe: output with read data, input with write data. | | |
C7 | Input/Output | DQ[1] | Data Input/Output: Bi-directional data bus | | |
C8 | Input/Output | DQ[3] | Data Input/Output: Bi-directional data bus | | |
C9 | Supply | VSSQ | DQ Ground | - | - |
D1 | Supply | VSSQ | DQ Ground | - | - |
D2 | Input/Output | DQ[6] | Data Input/Output: Bi-directional data bus | | |
D3 | Input/Output | ~DQS | Data Strobe: output with read data, input with write data. | | |
D7 | Supply | VDD | Power Supply | - | - |
D8 | Supply | VSS | Ground | - | - |
D9 | Supply | VSSQ | DQ Ground | - | - |
E1 | Supply | VREFDQ | Reference voltage for DQ | - | - |
E2 | Supply | VDDQ | DQ Power Supply | - | - |
E3 | Input/Output | DQ[4] | Data Input/Output: Bi-directional data bus | | |
E7 | Input/Output | DQ[7] | Data Input/Output: Bi-directional data bus | | |
E8 | Input/Output | DQ[5] | Data Input/Output: Bi-directional data bus | | |
E9 | Supply | VDDQ | DQ Power Supply | - | - |
F1 | | NC | No Connect | PIN_K22(648) | PIN_K22(648) |
F2 | Supply | VSS | Ground | - | - |
F3 | Input | ~RAS | Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. | | |
F7 | Input | CK | Clock: CK and ~CK are differential clock inputs. | | |
F8 | Supply | VSS | Ground | - | - |
F9 | | NC | No Connect | PIN_J22(639) | PIN_J22(639) |
G1 | Input | ODT | On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. | PIN_M21(645) | PIN_M21(645) |
G2 | Supply | VDD | Power Supply | - | - |
G3 | Input | ~CAS | Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. | | |
G7 | Input | ~CK | Clock: CK and ~CK are differential clock inputs. | | |
G8 | Supply | VDD | Power Supply | - | - |
G9 | Input | CKE | Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. | PIN_K24(582) | PIN_K24(582) |
H1 | | NC | No Connect | - | - |
H2 | Input | ~CS | Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. | | |
H3 | Input | ~WE | Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. | | |
H7 | Input | A[10]/AP | Address Input A[10] / Auto-precharge | | |
H8 | Supply | ZQ | Reference Pin for ZQ calibration | - | - |
H9 | | NC | No Connect | - | - |
J1 | Supply | VSS | Ground | - | - |
J2 | Input | BA[0] | Bank Address Input | | |
J3 | Input | BA[2] | Bank Address Input | | |
J7 | Input | A[15] | Address Input | | |
J8 | Supply | VREFCA | Reference voltage for CA | - | - |
J9 | Supply | VSS | Ground | - | - |
K1 | Supply | VDD | Power Supply | - | - |
K2 | Input | A[3] | Address Input | | |
K3 | Input | A[0] | Address Input | | |
K7 | Input | A[12]/~BC | Address Input A[12] / Burst Chop | | |
K8 | Input | BA[1] | Bank Address Input | | |
K9 | Supply | VDD | Power Supply | - | - |
L1 | Supply | VSS | Ground | - | - |
L2 | Input | A[5] | Address Input | | |
L3 | Input | A[2] | Address Input | | |
L7 | Input | A[1] | Address Input | | |
L8 | Input | A[4] | Address Input | | |
L9 | Supply | VSS | Ground | - | - |
M1 | Supply | VDD | Power Supply | - | - |
M2 | Input | A[7] | Address Input | | |
M3 | Input | A[9] | Address Input | | |
M7 | Input | A[11] | Address Input | | |
M8 | Input | A[6] | Address Input | | |
M9 | Supply | VDD | Power Supply | - | - |
N1 | Supply | VSS | Ground | - | - |
N2 | Input | ~RESET | Asynchronous Reset. Active Low | PIN_L20(654) | PIN_L20(654) |
N3 | Input | A[13] | Address Input | PIN_M27(417) | PIN_M27(417) |
N7 | Input | A[14] | Address Input | PIN_N21(630) | PIN_N21(630) |
N8 | Input | A[8] | Address Input | PIN_N22(627) | PIN_N22(627) |
N9 | Supply | VSS | Ground | - | - |
VDD - Power Supply: 1.35V +0.100/-0.067V
VDDQ - DQ Power Supply: 1.35V +0.100/-0.067V
4.6 J2 PCIe, FMC 8x20
FMC 8x20 pinout
| 160 | 159 | 158 | 157 | 156 | 155 | 154 | 153 | |
160 | | | PIN_AV26(2520) | POWER_ON (R682/10k to GND) | PIN_AW26(2511) | 12V | 12V | 12V | 153 |
152 | | PIN_AB28(2613) | PIN_AC28(2610) | | | GND | GND | 12V | 145 |
144 | | | | GND | | GND | | 12V | 137 |
136 | | GND | | GND | | GND | | GND | 129 |
128 | GND | | GND | | GND | GXB_TX_R8 | GND | GXB_TX_L0 | 121 |
120 | GND | | GND | | GND | GXB_TX_R8 | GND | GXB_TX_L0 | 113 |
112 | | GND | | GND | GXB_TX_R7 | GND | GXB_TX_L1 | GND | 105 |
104 | | GND | | GND | GXB_TX_R7 | GND | GXB_TX_L1 | GND | 97 |
96 | GND | | GND | | GND | GXB_TX_R6 | GND | GXB_TX_L2 | 89 |
88 | GND | | GND | | GND | GXB_TX_R6 | GND | GXB_TX_L2 | 81 |
80 | | GND | | GND | GXB_TX_R5 | GND | GXB_TX_L3 | GND | 73 |
72 | | GND | | GND | GXB_TX_R5 | GND | GXB_TX_L3 | GND | 65 |
64 | GND | | GND | | GND | GXB_TX_R3 | GND | GXB_TX_L5 | 57 |
56 | GND | | GND | | GND | GXB_TX_R3 | GND | GXB_TX_L5 | 49 |
48 | | GND | | GND | GXB_TX_R2 | GND | GXB_TX_L6 | GND | 41 |
40 | | GND | | GND | GXB_TX_R2 | GND | GXB_TX_L6 | GND | 33 |
32 | GND | | GND | | GND | GXB_TX_R1 | GND | GXB_TX_L7 | 25 |
24 | GND | | GND | | GND | GXB_TX_R1 | GND | GXB_TX_L7 | 17 |
16 | | GND | | GND | GXB_TX_R0 | GND | GXB_TX_L8 | GND | 9 |
8 | | GND | | GND | GXB_TX_R0 | GND | GXB_TX_L8 | GND | 1 |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |